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E2B0041-27-Y3 Semiconductor
Semiconductor MSM9000B-XX
DOT MATRIX LCD CONTROLLER
This version: Nov. 1997 MSM9000B-XX Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM9000B-XX is a dot-matrix LCD control driver which has functions of displaying 12 (5 x 7 dots) characters (2 lines) and 120-dot arbitrators. The MSM9000B-XX is provided with a 16-dot common driver, 60-dot segment driver, Display Data RAM (DDRAM), and Character Generator ROM (CGROM). This device can be controlled with commands entered through the serial interface or parallel interface. The font data in the CGROM can be changed by mask option. Since the MSM9000B-XX has an LCD driving bias generator circuit, LCD bias voltages can be obtained by merely providing a required capacitance externally. The MSM9000B-XX is applicable to a variety of LCD panels by controlling the contrast.
FEATURES
* Logic voltage(VDD): 2.5 to 3.3 V * LCD driving voltage(VBI) : 3.0 to 5.5 V * Low current consumption: 35 mA max.(operating) * Switchable between 8-bit serial interface and 8-bit parallel interface * Contains a 16-dot common driver and a 60-dot segment driver * Contains CGROM with character fonts of (5 x 7 dots) x 256 * Built-in bias voltage generator circuit * Built-in contrast adjusting circuit * Built-in 32.768 kHz crystal oscillator circuit * Provided with 120 dot arbitrators * 1/9 duty mode (1 line : characters, 2 lines : arbitrators) 1/16 duty mode (2 lines : characters, 2 lines : arbitrators) * Character blink operation can be switched between all-character lighting-on mode and allcharacter lighting-off mode. * Package: TCP mounting with 35 mm wide film ; Tin-plated (Product name : MSM9000B-XX AV-Z-xx) Chip (Product name : MSM9000B-XX) xx indicates code number.
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Semiconductor
MSM9000B-XX
BLOCK DIAGRAM
C1-C16 16 Common Regulator + Halver & Voltage Multiplier(4-fold) Latch 60 Shift Register VSS6 VSH VC1 VCC1 5 5 F/F Gate LCD bias Driver S1-S60 60 Segment Driver 60
VDD VSS VSS1 VSS2, 3 VSS4 VSS5 VC2 VCC2 N1 N2
Voltage Multiplier (3/2-fold)
Display Data RAM (DDRAM) (456 Bits)
8
Character Generator ROM (CGROM) (256 5 7 Dots)
XT XT 32K/EXT 9D/16D RESET TEST
Crystal OSC Circuit
Timing Circuit
8
Registers
I/O Interface 8 P/S CS C/D SHT SO SI WR RD DB7-0
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MSM9000B-XX
PIN CONFIGURATION
RESET 32K/EXT 9D/16D P/S XT XT VSS CS C/D RD WR SI SHT SO DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD TEST N1 N2 VCC1 VC1 VSH VSS6 VCC2 VC2 VSS1 VSS2, 3 VSS4 VSS5
COM1
COM8 SEG1 SEG2
SEG59 SEG60 COM16
COM9
Pin Configuration Viewed From Pattern
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MSM9000B-XX
PIN DESCRIPTIONS
Number of Pins 1 1 1 1 8 1 1 1 1 1 1 1 1 1 2 1 60 16 1 1 4 1 1 2 2 112
Function CPU Interface
Symbol CS WR RD C/D DB0-7 SI SO SHT
Type I I I I I/O I O I I O I I I I I I O O -- -- -- -- -- -- --
Description Chip select input signal Write enable signal, latch for serial interface Read enable signal Command/Data select input signal 8-bit parallel data inputs/outputs Serial data input Serial data output Shift clock input for data input in serial interface mode Crystal oscillation input, clock input Crystal oscillation output Parallel/Serial interface switching signal input Duty select signal input Clock select signal input Reset is performed by setting the RESET input to "L" level Contrast control signal input Test signal input. Fix to "L" Level or leave open Segment outputs for LCD driving Common outputs for LCD driving Positive + power supply pin for LOGIC GND pin Boosted voltage output pins & bias power supply pins Voltage multiplier output pin (3-/2-fold) Haver output pin Voltage multiplier (3-/2-fold) Voltage multiplier (4-fold)
Oscillation Control Signal
XT XT P/S 9D/16D 32K/EXT RESET N1, N2 TEST
LCD Driving Output Power Supply
SEG1-SEG60 COM1-COM16 VDD VSS VSS1, VSS2, 3 VSS4, VSS5 VSS6 VSH VC1, VCC1 VC2, VCC2 Total
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Bias voltage Input voltage Storage temperature Symbol VDD VBI VI TSTG Condition Ta=25C, VDD-VSS Ta=25C, VDD-VSS5 Ta=25C Chip TCP Rating -0.3 to +4.6 -0.3 to +7 -0.3 to VDD + 0.3 -55 to +150 -30 to +85 Unit V V V C Applicable pin VDD, VSS VDD, VSS5 All input pins --
Ta: Ambient temperature
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Bias voltage IC source oscillation Operating temperature Symbol VDD VBI fint Top Condition VDD-VSS *1, VDD-VSS5 *2 -- Range 2.5 to 3.3 3 to 5.5 26 to 47 -30 to +85 Unit V V kHz C Applicable pin VDD, VSS VDD, VSS5 *3 --
*1 VDD is the highest pin and VSS5 the lowest for the bias voltage. *2 Connect the specified capacitors to the voltage doubler and LCD bias generator. *3 Make sure that the crystal oscillation frequency or the divided clock frequency falls within this range. Note 1: Ensure the chip is not exposed to any light. Note 2: The bias voltage may exceed 5.5 V at some contrast stages. Adjust the stage with software so that the bias voltage does not exceed 5.5 V.
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = 2.5 to 3.3 V, VBI = 3 to 5.5 V, Ta = -30 to +85C) Parameter Input high voltage 1 Input high voltage 2 Input low voltage 1 Input low voltage 2 Input high current 1 Input high current 2 Input low current 1 Off leakage current Output high voltage 1 Output low voltage 1 COM output resistance SEG output resistance Drain current 1 Symbol VIH1 VIH2 VIL1 VIL2 IIH1 IIH2 IIL1 Ioff VOH VOL1 RC RS IDD1 Condition -- -- -- -- VI=VDD VI=VDD VI=0 V VI=VDD/0 V IO=-500 mA IO=500 mA IO=50 mA IO=20 mA During operation *1 Crystal oscillation f = 32.768 kHz During operation *1 Drain current 2 IDD2 External clock f = 32 kHz Drain current 3 IDD3 During standby -- -- 7 mA VDD -- 15 35 mA VDD -- 15 35 mA VDD Min. VDD-0.25 0.8VDD 0 0 -- 10 -1 -1 0.9VDD -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD VDD 0.55 0.2VDD 1 60 -- 1 -- 0.1VDD 10 30 Unit Applicable pin V V V V mA mA mA mA V V kW kW XT Other inputs XT Other input pins Input pins other than XT and TEST TEST (pull-down resistor) Input pins other than XT and TEST SO and DB0 to DB7 SO and DB0 to DB7 SO and DB0 to DB7 COM1 to COM16 SEG1 to SEG60
*1 No output load Note : The values in this table are assured when the chip is not exposed to light.
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Semiconductor DC Characteristics (2)
MSM9000B-XX
(VDD=0 V, VSS=-3 V, Ta=-30 to +85C) Parameter Bias voltage 1 Bias voltages 2 and 3 Bias voltage 4 Bias voltage 5 Contrast pitch Symbol -VSS1 -VSS2, 3 -VSS4 -VSS5 -Vcon Condition -VSS2, 3 = "A"V N1 = "L", N2 = "L" Contrast = "5" -VSS2, 3 = "A"V -VSS2, 3 = "A"V VBI for each stage Min. 1/2A-0.1 1.9 3/2A-0.1 2A-0.2 0.18 Typ. 1/2A 2.2 3/2A 2A 0.21 Max. 1/2A+0.1 2.5 3/2A+0.1 2A+0.2 0.26 Unit Applicable pin V V V V V VSS1 VSS2, 3 VSS4 VSS5
--
Note 1: Connect a 0.1 F capacitor to the LCD bias generator. Note 2: The values in this table are assured when the chip is not exposed to light.
AC Characteristics Parallel interface
(VDD=2.5 to 3.3 V, VBI=3 to 5.5 V, Ta=-30 to +85C) Parameter RD high-level width RD low-level width WR high-level width WR low-level width WR-RD high-level width CS or C/D setup time CS or C/D hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock high-level width External clock low-level width RESET pulse width Rise and fall time of external clock Symbol tWRH tWRL tWWH tWWL tWWRH tAS tAH tDSW tDHW tDDR tDHR tWCH tWCL tWRE tr, tf Condition -- -- -- -- -- -- -- -- -- CL=50 pF -- -- -- -- -- Min. 200 200 200 200 200 50 0 50 50 -- 20 1 1 2.0 -- Max. -- -- -- -- -- -- -- -- -- 200 -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns
Note: The values in this table are assured when the chip is not exposed to light.
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Semiconductor Serial interface
MSM9000B-XX
(VDD = 2.5 to 3.3 V, VBI = 3 to 5.5 V, Ta = -30 to +85C) Parameter CS or C/D setup time CS or C/D hold time SI setup time SI hold time SHT high-level pulse width SHT low-level pulse width SHT clock cycle time SO ON delay time SO output delay time SO OFF delay time BUSY delay time WR setup time WR low-level pulse width RESET pulse width Rise and fall time of external clock Symbol tSAS tSAH tIS tIH tWSHH tWSHL tSYS tON tDS tOFF tBUSY tSHS tWWL tWRE tr, tf Condition -- -- -- -- -- -- -- CL= 50 pF CL= 50 pF -- CL= 50 pF -- -- -- -- Min. 100 20 100 20 100 100 400 -- 0 -- -- 200 120 2.0 -- Max. -- -- -- -- -- -- -- 200 200 100 200 -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
Note: The values in this table are assured when the chip is not exposed to light.
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Semiconductor Timing Diagram for the Parallel Interface
MSM9000B-XX
CS
VIH VIL
-- --
C/D
VIH VIL
-- --
tAS
tWWL
tAH
tAS
tAH
WR
VIH VIL
-- --
tWWH tWWRH tWRH tWRL
RD
VIH VIL
-- --
tDSW VIH DB0-7 VIL tWRE
tDHW
tDDR VOH VOL
tDHR
RESET VIL
--
tr
tf
tWCH
XT
VIH VIL
-- --
tWCL
VIH = 0.8VDD, VOH = 0.9VDD,
VIL = 0.2VDD VOL = 0.1VDD
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Semiconductor Timing Diagram for the Serial Interface
MSM9000B-XX
CS
VIH VIL VIH VIL VIH VIL
-- --
C/D
-- --
tSAH
-- --
SI
tSAS VIH VIL
--
tIS
tIH
SHT
50%
--
tWSHL VIH VIL
--
tWSHH
tSHS
WR
tSYS
--
tON VOH VOL
-- --
tDS
tWWL
tBUSY
tOFF "Z"
"Z"
SO
tWRE
RESET VIL
--
tr
tf
XT
VIH VIL
-- --
VIH = 0.8 VDD, VOH = 0.9 VDD,
VIL = 0.2 VDD VOL = 0.1 VDD
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FUNCTIONAL DESCRIPTION
Pin Functional Description * CS (Chip Select) Chip select input pin. A logic low on the CS input selects the chip and a logic high on the CS input does not select the chip. Command and display data inputs can be enabled only when the chip is selected. When the input is high, the SO pin and DB0 to DB7 pins are in the high impedance state, causing SHT, WR and RD pins high level internally. * WR (Write Enable) When the parallel interface is used, this pin is the write signal input. Data is written into the register at the rising edge of WR pulse. When the serial interface is used, this pin is the latch signal input. This pin is normally high. * RD (Read Enable) When the parallel interface is used, this pin is the read signal input. While the pulse is low, data can be read. The pin is normally high. When this pin is made low with C/D set low, the display data pointed to by the address pointer is output from DB0 to DB7. When the pin is made low with C/D set high, busy data is output from DB0 and low signals are output from DB1 to DB7. After the rising edge of WR, busy data (H) is output. The data automatically changes to non-busy (L) after the specified time elapses. When the serial interface is used, fix this pin to "H" or "L". * C/D (Command/Data Select) This input pin selects whether the data to be input to the SI pin and the DB7 to DB0 pins is handled as a command or display data, depending on the state of the pin at the rising edge of WR. When the pin is H, the input data is handled as a command. When the pin is L, display data is input. * DB0 to DB7 (Data Buses 0 to 7) Data input and output pins for the parallel interface. Normally data buses 0 to 7 are in high impedance, when RD is driven low, display data and the busy signal are output. When the serial interface is used, leave this pin open. * SI (Serial Data Input) Data input pin for the serial interface. Commands and display data are read at the rising edge of SHT and written to registers at the rising edge of WR. The eight-bit data immediately before the rising edge of WR is valid. When the parallel interface is used, fix this pin to "H" or "L". * SO (Serial Data Output) Data output pin for the serial interface. The display data pointed to by the address pointer is output at the rising edge of SHT. After the rising edge of WR, busy data (H) is output. The data automatically changes to non-busy (L) after the specified time elapses. When the parallel interface is used, this pin remains in the high impedance state. * SHT (Shift Clock) Clock input pin to input and output serial interface data. Data input is synchronous with the rising edge of the clock, and the data output is synchronous with the falling edge of the clock. This pin is normally high. When the parallel interface is used, fix this pin to "H" or "L". 11/38
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MSM9000B-XX
* XT (Crystal) Input pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this pin and the XT pin, a crystal oscillation circuit is formed. When an external clock is used, input the clock to the XT pin. * XT (Crystal) Output pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this pin and the XT pin, a crystal oscillation circuit is formed. When the external clock is used, leave this pin open.
XT 18 pF XT 32.768 kHz XT OPEN XT External clocks
18 pF
When forming a crystal oscillation circuit
When inputting an external clock
Oscillation circuit diagram * P/S (Parallel/Serial Select) Input pin to choose between the parallel interface and serial interface. To select the parallel interface, make this pin low. To select the serial interface, make this pin high. After power is turned on, do not change the setting of this pin. * 9D/16D (Duty Select) Input pin to set a duty cycle. When this pin is set to "H", a duty cycle of 1/9 is selected. When the pin is set to "L", a duty cycle of 1/16 is selected. Choose either according to the panel to be used. When a duty cycle of 1/9 is chosen, leave common output pins COM10 to COM16 open. * 32K/EXT (Clock Select) Input pin to choose crystal oscillation mode or external clock input mode. Leave this pin at a "L" level. * RESET (Reset) Reset signal input pin. Setting this pin to L results in the initial state. For modes and the display after a reset input, see "Mode Settings after a Reset Input". * N1, N2 (Contrast Change) Input pins that determine the voltages of VSS2 and VSS3 together with contrast adjustment by a command. The table below shows the relationships between pin states and contrast adjustment ranges.
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N1 L L H H
N2 L H L H
Contrast adjustment range by command 0 to 7 1 to 8 2 to 9 3 to A
* TEST (Test Signal) Test signal input pin provided for test by the manufacturer. Fix this pin to L or leave it open. * SEG1 to SEG60 (Segment 1 to Segment 60) Segment signal output pins to drive the LCD. Leave the unused pins open. * COM1 to COM16 (Common 1 to Common 16) Common signal output pins to drive the LCD. When the duty cycle is 1/9, use COM1 to COM9 and leave COM10 to COM16 open. * VDD Power supply pin to the logic section. Connect this pin to the positive terminal on the power supply. * VSS Pin to be connected to the GND power supply. * VSS1, VSS4, VSS5 Pins for voltage multiplier outputs and LCD power supply. Connect capacitors of 0.1 F between these pins and VDD for the charge distribution with VSS2, 3 capacitor and for voltage stabilization during generation of LCD bias voltages. The logical values of the LCD bias voltage are as follows: Highest voltage: VDD VSS1=VSS2, 3/2 VSS2, 3 VSS4=VSS2, 3+VSS2, 3/2 Lowest voltage: VSS5=VSS2, 3+VSS2, 3/2+VSS2, 3/2 For both the 1/9 and 1/16 duty, 1/4 bias is used. * VSS2, 3 Voltage regulator output pin & LCD bias generator input used as a reference voltage for the LCD bias generator. Connect a capacitor of 0.1 F between this pin and VDD for charge distribution among capacitors and voltage stabilization during generation of various LCD bias voltages. * VSS6 Pin to connect the capacitor to store the 3-/2-fold voltage. Connect a capacitor of 0.1F or more between this pin and VDD. * VSH Halves output pin for the voltage multiplier(3-/2-fold). Connect a 0.1 F capacitor between this pin and VDD. 13/38
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MSM9000B-XX
* VC1, VCC1 Pins to connect the charge distribution capacitor used for the voltage malitiplier (3-/2-fold). Connect a 0.1 F capacitor between VC1 and VCC1. * VC2, VCC2 Pins to connect the capacitor for charge distribution to generate LCD bias voltages on the basis of VSS2, 3. Connect a 0.1 F capacitor between VC2 and VCC2.
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Semiconductor Parallel Interface Input-Output Timing Input timing diagram
MSM9000B-XX
CS
C/D
DB7-0
DATA
WR
Output timing diagram
CS
C/D
"L"
"H"
RD
DB7-1
DATA
"L"
DB0
DATA
BUSY
When C/D="L", RAM display data is output on DB7-0 pins. When C/D="H" and DB7-1="L", busy data is output on DB0 pin.
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Semiconductor I/O Timings on the Serial Interface Input timing diagram
MSM9000B-XX
CS
C/D
SHT
SI
D7
D6
D5
D4
D3
D2
D1
D0
WR
Output timing diagram
CS
C/D
SHT
SO
BUSY
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
WR
In SO output, the eight bits after the WR pulse is input are valid.
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LIST OF COMMANDS
*: Don't Care No Mnemonics 1 LPA Operation Load Pointer Address 2 3 4 LOT SF BKCG 1/0 Load Option Set Frequency Bank Change 1/0 1 1 1 0 0 0 1 1 0 1 0 * * * 0 * * 0 I1 F1 0 I0 F0 D 7 1 6 1 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0 Comments Addresses 0-11, 16-27 for characters and addresses 32-43, 48-59 for arbitrators Sets additional functions during execution of AINC. Sets conditions on master frequency.
1/0 Valid only in 1/9 duty. Changes display addresses 0-11, 16-27.
5
CONT U/D
Contrast Up/Down
1
0
0
*
0
0
1
1/0 Adjusts VLCD to 8 stages. Adjustment range is changed by setting N1 and N2 pins. Contrast level is up if D0="1". Contrast level is down if D0="0".
6
STOP
Set Stop Mode
1
0
0
*
0
1
0
0
This mode is cancelled if D0="1" irrespective of either "H" or "L" on C/D. Stops oscillation and performs operation equivalent to that of the DISP OFF command.
7
SOE/D
Serial Out Enable/Disable
1
0
0
*
0
1
1
1/0 Switches between output and high impedance of SO.
8
DISP
Display On/Off
1
0
0
1/0
1
0
0
1/0 Display is ON if D0="1". Display is OFF if D0=0. All commons and segments are at VDD level if display is OFF. Arbitrators alone are displayed if D4="1".
9
AINC
Address Increment
1
0
0
*
1
0
1
*
Pointer address is incremented by 1. But, this command is invalid to operations that are added by setting (I1, I0).
10
ABB
Arbitrator Blink
1
0
0
*
1
1
0
1/0 Data that is input after setting D0="1", is set as data for arbitrator blink (1-dot unit). This is cancelled by D0="0".
11 12
CHB BPC
Character Blink Blink Pattern Control
0 1
0 0
0 0
* *
0 1
0 1
1/0 1
*
Controls blinking of character.
1/0 Sets blink patterns of characters. ( : chara) if D0="1", ( : chara) if D0="0".
13
ABLC
Arbitrator Line Change
0
1
1
*
*
*
L1
L0
Sets arbitrator display lines.
Notes :1 Pointer address is not changed even if commands numbers 1 to 8, 10, 12, 13 are enterd. :2 Pointer address is automatically incremented by 1 when commands numbers 9, 11, display code data, and arbitrator data are enterd.
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Semiconductor * LOT
I1 0 0 1 1 I0 0 1 0 1 Additional function No additional function A blank code is written for each subsequent AINC. Blinking is canceled for each subsequent AINC. The above two functions are ORed.
MSM9000B-XX
Remarks Used to automatically clear RAM at power-on.
* SF
F1 0 0 1 1 F0 0 1 0 1 Frequency of source oscillation in the IC XT XT 2 XT 4 XT 8 clocks are input. Remarks Used to generate the optimum frequency when external
* DISP
D4 * 0 1 D0 0 1 1 Character OFF ON OFF Arbitrator OFF ON ON Remarks Used to turn on and off the display.
* : Don't care * ABLC (when the duty is 1/16)
L1 0 0 1 L0 0 1 * Arbitrator 1 COM1 COM15 COM16 Arbitrator 2 COM2 COM16 COM1 Remarks Arbitrator 1 indicates display data at addresses 32 to 43, while arbitrator 2 indicates display data at addresses 48 to 59.
* : Don't care * ABLC (when the duty is 1/9)
L1 0 0 1 L0 0 1 * Arbitrator 1 COM1 COM8 COM9 Arbitrator 2 COM2 COM9 COM1 Remarks Arbitrator 1 indicates display data at addresses 32 to 43, while arbitrator 2 indicates display data at addresses 48 to 59.
* : Don't care
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Explanation of Commands [D7, D6, D5, D4, D3, D2, D1, D0], X = Don't care * LPA (Load Pointer Address) [1, 1, A5, A4, A3, A2, A1, A0] This command sets in the address pointer the address of the command to be executed or the address of the display data to be input. The settable addresses are inconsecutive addresses 00H to 0BH, 10H to 1BH, 20H to 2BH, 30H to 3BH represented by A5 to A0. When addresses 0CH to 0FH, 1CH to 1FH, 2CH to 2FH, or 3CH to 3FH are set, 00H is assumed. After RESET = "L", the address is set to 00H. * LOT (Load Option) [1, 0, 1, 1, X, X, I1, I0] This command executes the additional function specified by I1 and I0 to the display of the current address when the AINC command is executed. Additional functions are shown below. After RESET = "L",, both I1 and I0 are set to "0".
I1 0 0 1 1 I0 0 1 0 1 None After this command is executed, the blank code is writtern each time AINC is executed. After this command is executed, blinking is canceled each time AINC is executed. The above two additional functions are ORed. Additional function
* SF (Set Frequency) [1, 0, 1, 0, X, X, F1, F0] This command sets the number by which the external clock input from the XT pin is divided in order to get the source frequency inside the IC. This command is valid when 32K/EXT pin is "L". The dividing ratio is specified by F1 and F0 in the command. The table below lists the source oscillation frequencies in the IC. After RESET = "L", both F1 and F0 are set to "0".
F1 0 0 1 1 F0 0 1 0 1 Frequency of source oscillation in the IC XT XT 2 XT 4 XT 8
* BKCG1/0 (Bank Change 1/0) [1, 0, 0, X, 0, 0, 0, 1/0] This command changes addresses (banks) to be displayed. The command is valid only when the duty is 1/9. When D0 is 0, addresses 0 to 11 (character 1), 32 to 43, and 48 to 59 (arbitrators 1 and 2) are displayed. When D0 is "1", addresses 16 to 27 (character 2), 32 to 43, and 48 to 59 (arbitrators 1 and 2) are displayed. The command and display data can be set regardless of the bank setting. After RESET = "L", D1 is set to "0".
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* CONT U/D (Contrast Up Down) [1, 0, 0, X, 0, 0, 1, 1/0] This command selects the voltage of VSS2, 3 that is used as the reference voltage for the LCD bias. When the value of VSS2, 3 is changed, the contrast is changed accordingly. The contrast is controlled by the value of the 3-bit up/down counter so that eight stages are supported. The value of the up/down counter is incremented when "1" is entered by this command and decremented when "0" is entered. The counter changes within the range of 0 to 7. When the counter reaches 7, it goes back to "0". According to the settings of N1 and N2, the contrast stages can be changed to 1 to 8, 2 to 9, or 3 to A. At stage 0, the bias voltage is minimized. The larger the contrast stage, the higher the bias voltage. At stage A, the bias voltage is maximized. After a low RESET is input, the counter is set to the minimum value specified by N1 and N2. Example: * * * 67012345670 * * * Note: At some contrast stages, the bias voltage may be increased to 5.5 V or higher. Adjust the stage so that the bias voltage does not exceed 5.5 V. * STOP (Set Stop Mode) [1, 0, 0, X, 0, 0, 1, 0] This command sets standby mode. Specifically, the command stops the oscillation block to prevent current form flowing through the oscillation block and outputs the VDD level to all LCD output pins. Standby mode is canceled when D0 is set to "1" regardless of the setting of the C/D pin. When a command or data with D0 set to "1" is entered, the command is executed or the data is input. At the same time, standby mode is canceled. After RESET = "L", standby mode is disabled. * SOE/D (Serial Out Enable/Disable) [1, 0, 0, X, 0, 1, 1, 1/0] This command controls the impedance of the SO output pin. The command is valid only when the serial interface is used. When D0 is set to "0", the SO pin is set in the high impedance state. After RESET = "L", D0 is set to "0". * DISP (Display On/Off) [1, 0, 0, 1/0, 1, 0, 0, 1/0] This command sets LCD display mode. When D0 is set to "1", the LCD is turned on. When D0 is set to "0", the LCD is turned off, in which case, the VDD level is output to all segment and common pins. When the LCD is turned ON (D0="1"), and D4 is set to "1", only arbitrators are displayed and when D4 is set to "0", both characters and arbitrators are displayed. The table below lists display modes. After RESET = "L", both D4 and D0 are set to "0".
D4 X 0 1 D0 0 1 1 Characters OFF ON OFF Arbitrators OFF ON ON
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Semiconductor
MSM9000B-XX
* AINC (Address Increment) [1, 0, 0, X, 1, 0, 1, X] This command increments the value of the address pointer by one. Each time this command is input, the value is incremented by one. Addresses are increased as follows: 00 to 11 AE 16 to 27 AE 32 to 43 AE 48 to 59 AE 00 ***. This cycle is repeated. The function specified by the LOT command is performed for the previous address before the address incremented by one every time this command is input. * ABB (Arbitrator Blink) [1, 0, 0, X, 1, 1, 0, 1/0] This command turns arbitrator blinking on or off. Display data input after D0 is set to "1" is handled as arbitrator blink data. Input blink data corresponds to dots of the arbitrator at the same address on a one-to-one basis. When the dot is "1", blinking is enabled. When the dot is "0", blinking is disabled. While the dot is blinking, it is turned on and off repeatedly. Blinking can be specified for a dot for which enabling the arbitrator is not specified, but the dot does not blink. Dummy data must be set for arbitrator data D5 to D7. Data cannot be written to addresses 00 to 31 and 44 to 47. After RESET = "L", D0 is set to "0". * CHB (Character Blink) [0, 0, 0, X, 0, 1, 1/0, X] This command enables or disables character blinking. The command is executed for the address pointed to by the address pointer. When D1 is set to "1", blinking is enabled. When D1 is set to "0", blinking is disabled. During blinking, the turning on of all dots (5 7 dots) and character display are repeated. In another blinking pattern, the turning off of all dots and character display are repeated. Either pattern is selected by the BPC command. After RESET = "L", the value of the address pointer is automatically incremented by one. * BPC (Blink Pattern Control) [1, 0, 0, X, 1, 1, 1, 1/0] This command selects a character blinking pattern. When D0 is set to "1", the turning on of all dots (5 7 dots) and character display are repeated. When D0 is set to "0", the turning off of all dots and character display are repeated. When D0 is "1" but the character is a blank, the character does not blink visibly. When D0 is "0", the character does not blink visibly while all its dots are turned on. After RESET = "L", D0 is set to "0".
[D0 = "1"]
[D0 = "0"]
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Semiconductor
MSM9000B-XX
* ABLC (Arbitrator Line Change) [0, 1, 1, X, X, X, L1, L0] This command selects a common line for arbitrator display, according to the settings of L1 and L0. The table below shows the relationships between L1 and L0 and displayed common lines, assuming that the display data at addresses 00 to 11 is character 1, the display data at addresses 16 to 27 is character 2, the display data at addresses 32 to 43 is arbitrator 1, and the display data at addresses 48 to 59 is arbitrator 2. Different common lines are displayed for 1/ 16 duty and 1/9 duty. After a low RESET is input, both L1 and L0 are set to "0". Common lines displayed by the ABLC command are as follows: When 1/16 duty is chosen
L1 0 0 1 L0 0 1 X Character 1 COM3 to 9 COM1 to 7 COM2 to 8 Character 2 COM10 to 16 COM8 to 14 COM9 to 15 Arbitrator 1 COM1 COM15 COM16 Arbitrator 2 COM2 COM16 COM1
When 1/9 duty is chosen
L1 0 0 1 L0 0 1 X Character 1 COM3 to 9 COM1 to 7 COM2 to 8 Character 2 Arbitrator 1 COM1 COM8 COM9 Arbitrator 2 COM2 COM9 COM1
Note: When 1/9 duty is chosen, characters 1 and 2 can be switched by changing the bank. * Increment of the address pointer by one When display data or arbitrator blink data is input or the AINC or CHB command is executed, the address pointer is incremented by one.
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Semiconductor
MSM9000B-XX
Mode Setting after a Reset Input The table below lists the settings of individual modes during a RESET =L input.
Command LPA LOT SF BKCG 1/0 CONT U/D STOP SOE/D DISP ABB BPC ABLC D0 = "0" D4 = "0", D0 = "0" D0 = "0" D0 = "0" L1 = "0", L0 = "0" Mode setting A5 to A0 = "0" I1 = "0", I0 = "0" F1= "0", F0 = "0" D0 = "0" -- -- Remarks The address pointer is set to "00". Load Option command with no additional function. The dividing ratio is set to 1. Display addresses 00 to 11 are set. The control counter is set to 0 (Stage 0). Standby mode is disabled. The SO pin is set to the high impedance state. Both characters and arbitrators display mode is set, but the dispaly is turned off. Display data input mode is enabled. Blink mode is such that the turning on of all dots and character display are repeated. Arbitrator 1 corresponds to COM1, and arbitrator 2 corresponds to COM2.
* Even when a reset is input, display RAM is not initialized. To clear the display data, a blank code must be written. (This can be done with an additional function of the AINC command.)
Mode Settings during Standby The table below lists the settings of individual modes during standby.
Command LPA LOT SF BKCG 1/0 CONT U/D STOP SOE/D DISP ABB BPC ABLC No change The setting before standby mode is retained. D0 = "0" D4 = "0", D0 = "0" -- -- The count before standby mode is retained. Standby state 10. No change. The setting before standby mode is retained. Both character and arbitrator display mode is set, but the display is turned off. No change The setting before standby mode is retained. Mode setting A5 to A0 = "0" Remarks The address pointer is set to "00".
* Data before standby mode is retained in display RAM.
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Semiconductor Display Screen and Memory Addresses
MSM9000B-XX
Arbitrator 1 Arbitrator 2 Character 1 Screen Character 2
32 48 RAM map 0 16
33 49 1 17
42 58 10 26
43 59 11 27
Arbitrator 1 Arbitrator 2 Character 1 Character 2
Note: Characters are input as codes. Arbitrators are displayed directly without intervening CG ROM. Input data is displayed as shown below.
S5n+1
S5n+5
S: Segment n: 0 to 11
D4
D0
Dummy data must be set for input data D7 to D5. Either "1" or "0" can be input as input data of D7 to D5.
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Semiconductor Calculation Method of Various Kinds of Frequencies * Frame frequency For 1/16 duty (Source clock cycle) (1/Dividing ratio) 448 = Frame cycle * * * * * (1) For 1/9 duty (Source clock cycle) (1/Dividing ratio) 468 = Frame cycle * * * * * (2) Example Source oscillation frequency = 32.768 kHz Dividing ratio = 1/1 Specification: 1/16 Duty Clock cycle Ts = 30.5 s
MSM9000B-XX
Under these conditions, the frame frequency can be calculated from expression (1) as follows: Frame cycle Tf = 30.5 10-6 1 448 = 13.66 ms Therefore Frame frequency = 73.2 Hz * Calculating the blinking frequency The blinking frequency can be calculated from the following expression: Blinking frequency = (Source clock cycle) (1/Dividing ratio) 215 * * * * * (3) Example Source oscillation frequency = 32.768 kHz Dividing ratio = 1/1 Clock cycle TS = 30.5 s Under these conditions, the blinking frequency can be calculated from expression (3) as follows: Blinking cycle Tf = 30.5 10-6 1 215 = 1 s Therefore Blinking frequency = 1 Hz * Source oscillation frequency and busy time When data is written to or read from RAM or a command is input, data processing time (busy time) is taken. The maximum busy time is the source clock cycle multiplied by 10. The busy signal (not-busy = "L", busy = "H" ) is detected at the SO pin when the serial interface is used or at the DB0 pin when the parallel interface is used. When display data or commands are input consecutively, a wait must be inserted for the source clock cycle multiplied by 10. Another way is to detect busy signals and input data or commands during not-busy time only.
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Semiconductor Flowchart at Power-on (parallel interface)
MSM9000B-XX
Turn on the power Input a reset CS="L" Set modes for SF, BKCG1/0, BPC, and ABLC LOT, I1="1", I0="1" AINC 48 times LOT, I1="0", I0="0"
Input a reset after the VDD-VSS level exceeds 2.5V. 5ms, external, or power-on reset Chip enable.
Set a mode by the reset input according to specifications. Set the load option. The blank code is written and blinking is released each time AINC is executed. RAM data is cleared. The load option is cleared.
Input data to be displayed on the initial screen
NO
Has data to be displayed on the initial screen been input? YES DISP, D4="X", D0="1" Perform ordinary operation The display is turned on. The initial screen is displayed. Set D4 according to the display.
* When the stage to be selected is already determined, contrast can be adjusted before the display is turned on (for example, at the same time as when mode is set). * After a command or display data is input, check for busy data. Make sure that the busy data ("H") has changed to not-busy data ("L") before making the next input.
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Semiconductor Flowchart at Power-on (serial interface)
MSM9000B-XX
Turn on the power Input a reset CS="L" SOE/D, D0="1" Wait for 10 clocks Set modes for SF, BKCG1/0, BPC, and ABLC LOT, I1="1", I0="1" AINC 48 times LOT, I1="0", I0="0"
Input a reset after the VDD-VSS level exceeds 2.5V. 5ms, external, or power-on reset Chip enable. SO output is enabled to detect busy signal. Insert a wait only in processing the SOE/D command. (By busy signal detection for subsequent inputs).
Change the settings after a reset, if necessary. Set the load option. The blank code is written and blinking is disabled each time AINC is executed. RAM data is cleared. The load option is cleared.
Input data to be displayed on the initial screen
NO
Has data to be displayed on the initial screen been input? YES DISP, D4="X", D0="1" Perform ordinary operation The display is turned on. The initial screen is displayed. Set D4 according to the display.
* When the stage to be selected is already determined, contrast can be adjusted before the display is turned on (for example, at the same time as when mode is set). * After a command or display data is input, check for busy data. Make sure that the busy data ("H") has changed to not-busy data ("L") before making the next input.
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Semiconductor
MSM9000B-XX
Flowcharts to Set and Cancel Standby Mode
Ordinary operation
Busy signal detection
Confirm not-busy signal.
NO
Not-busy?
YES STOP Standby mode Set standby mode.
Standby mode Set D0 to 1. Wait until oscillation is stabilized. Wait until voltage multiplier is stabilized. Ordinary operation The length of the wait depends on the configuration of the oscillation circuit. When the code in which D0 is set to 1 is input, standby mode is canceled regardless of C/D input.
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Semiconductor Liquid Crystal Applied Waveform Examples In 1/16 duty
MSM9000B-XX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
C1
C2
C16
VDD VSS1 VSS2, 3 VSS4 VSS5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD VSS1 VSS2, 3 VSS4 VSS5
Sn
= Lighting-on = Lighting-off
29/38
Semiconductor In 1/9 duty
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7
MSM9000B-XX
8
9 VDD VSS1 VSS2, 3 VSS4 VSS5 VDD VSS1 VSS2, 3 VSS4 VSS5
C1
C2
C9
VDD VSS1 VSS2, 3 VSS4 VSS5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 VDD VSS1 VSS2, 3 VSS4 VSS5
Sn
= Lighting-on = Lighting-off
30/38
Semiconductor Codes and Character Fonts of Code -01
00H : 08H : 10H : 18H : 20H : SP 28H : ( 30H : 0
MSM9000B-XX
38H : 8
01H :
09H :
11H :
19H :
21H : !
29H : )
31H : 1
00H : 9
02H :
0AH :
12H :
1AH :
22H : "
2AH :
32H : 2
3AH : :
03H :
0BH :
13H :
1BH :
23H : #
2BH : +
33H : 3
3BH : ;
04H :
0CH :
14H :
1CH :
24H : $
2CH : ,
34H : 4
3CH : <
05H :
0DH :
15H :
1DH :
25H : %
2DH : -
35H : 5
3DH : =
06H :
0EH :
16H :
1EH :
26H : &
2EH : .
36H : 6
3EH : >
07H :
0FH :
17H :
1FH :
27H : '
2FH : /
37H : 7
3FH : ?
31/38
Semiconductor
MSM9000B-XX
40H : @
48H : H
50H : P
58H : X
60H :
68H : h
70H : p
78H : x
41H : A
49H : I
51H : Q
59H : Y
61H : a
69H : i
71H : q
79H : y
42H : B
4AH : J
52H : R
5AH : Z
62H : b
64H : j
72H : r
7AH : z
43H : C
4BH : K
53H : S
5BH : [
63H : c
6BH : k
73H : s
7BH : {
44H : D
4CH : L
54H : T
5CH : /
64H : d
6CH : I
74H : t
7CH :
45H : E
4DH : M
55H : U
5DH : ]
65H : e
6DH : m
75H : u
70H : }
46H : F
4EH : N
56H : V
5EH : ^
66H : f
6EH : n
76H : v
7EH : ~
47H : G
4FH : O
57H : W
5FH : _
67H : g
6FH : o
77H : w
7FH :
32/38
Semiconductor
MSM9000B-XX
8OH : A
88H : a
9OH : n
98H :
A0H :
A8H :
B0H : --
B8H :
81H : A
89H : a
91H : o
99H : i
A1H :
49H :
B1H :
B9H :
82H : AE
8AH : a
92H : U
9AH :
A2H :
AAH :
B2H :
BAH :
83H : C
8BH : a
93H : u
9BH :
A3H :
ABH :
B3H :
BBH :
84H : E
8CH : ae
94H : a
9CH :
A4H :
aCH :
B4H :
BCH :
85H : N
8DH : c
95H : b
9DH :
A5H :
ADH :
B5H :
BDH :
86H : O
8EH : e
96H : O
9EH :
A6H :
AEH :
B6H :
BEH :
87H : U
8FH : e
97H : o
9FH :
27H :
2FH :
37H :
3FH :
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Semiconductor
MSM9000B-XX
COH :
C8H :
DOH :
D8H :
EOH :
E8H :
FOH : G
F8H : e
C1H :
C9H :
D1H :
D9H :
E1H :
E9H : O
F1H :
F9H : l
C2H :
CAH :
D2H :
DAH :
E2H :
EAH :
F2H : q
FAH : p
C3H :
CBH :
D3H :
DBH :
E3H :
EBH :
F3H : X
FBH : s
C4H :
CCH :
D4H :
DCH :
E4H :
ECH :
F4H : S
FCH : u
C5H :
CDH :
D5H :
DDH :
E5H :
EDH :
F5H : F
FDH :
C6H :
CEH :
D6H :
DEH :
E6H : AE
EEH :
FEH : Y
FEH :
C7H :
CFH :
D7H :
DFH :
E7H :
EFH :
F7H : W
FFH :
34/38
Semiconductor
MSM9000B-XX
APPLICATION CIRCUITS
Example 1 [1/16 duty, parallel interface, crystal oscillation circuit and bias voltage generator used]
LCD Panel
5 x 7 dot characters x 12 characters x 2 lines 60 symbols x 2 lines
VDD VDD C VDD C C C VC1 C C=0.1 mF C C VDD C VCC1 VC2 VCC2 VSH VSS1 VSS2, 3 VSS4 VSS5
16 common drivers
60 Segment drivers
C1 to C16
S1 to S60 XT
18 pF 18 pF XT 32.768 kHz 32K/EXT 9D/16D
MSM9000B-XX
P/S
100 kW RESET 1 mF
DB7-0 CS WR RD C/D
VSS6 VSS 8 PORT
SI SO SHT
TEST N1 N2
OPEN VDD or VSS VDD or VSS
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Semiconductor
MSM9000B-XX
Example 2 [1/9 duty, serial interface, 32kHz external clock input and bias voltage generator used]
LCD Panel
5 x 7 dot characters x 12 characters x 1 line 60 symbols x 2 lines
VDD VDD C VDD C C C VC1 C C=0.1 mF C C VDD C VCC1 VC2 VCC2 VSH VSS1 VSS2, 3 VSS4 VSS5
9 common drivers
OPEN 7
60 Segment drivers
C1 to C9
C10 to C16
S1 to S60 XT XT 32K/EXT 32 kHz External Clock OPEN
MSM9000B-XX
9D/16D P/S
100 kW RESET 1 mF
DB7-0
VSS6 VSS 8
SHT
TEST N1 N2
C/D
WR
RD
OPEN PORT
SO
CS
SI
VDD or VSS VDD or VSS
36/38
Semiconductor
MSM9000B-XX
PAD CONFIGURATION
Pad Layout Chip size: 4.76 3.29 mm Bump size: 78 100 mm
Y 87 88 50 49
X
112 1 24
25
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name VSS CS C/D RD WR SI SHT SO DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD TEST N1 N2 X (m) -2012 -1837 -1662 -1487 -1312 -1137 -962 -787 -612 -437 -262 -88 88 262 437 612 787 962 1137 1312 Y (m) -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 -1508 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name VCC1 VC1 VSH VSS6 VCC2 VC2 VSS1 VSS2,3 VSS4 VSS5 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG60 SEG59 X (m) 1487 1662 1837 2012 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 2194 Y (m) -1508 -1508 -1508 -1508 -1375 -1255 -1135 -1015 -895 -775 -605 -495 -385 -275 -165 -55 55 165 275 385
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Semiconductor
MSM9000B-XX
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pad Name SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19
X (m) 2194 2194 2194 2194 2194 2194 2194 2194 2194 1980 1872 1765 1659 1552 1444 1337 1231 1123 1016 910 803 695 588 482 374 267 161 54 54 -161 -267 -374 -482 -588 -695 -803 -910 -1016 -1123 -1231
Y (m) 495 605 715 825 935 1045 1155 1265 1375 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508 1508
Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
Pad Name SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 RESET 32K/EXT 9D/16D P/S XT XT
X (m) -1337 -1444 -1552 -1659 -1765 -1872 -1980 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194 -2194
Y (m) 1508 1508 1508 1508 1508 1508 1508 1375 1265 1155 1045 935 825 715 605 495 385 275 165 55 -55 -165 -275 -385 -495 -605 -775 -895 -1015 -1135 -1255 -1375
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